Transistor structures have been proposed for modifying the amount of stress existing in a channel region. A known problem in the art is the depletion of dopants in a polysilicon gate electrode at the end to the channel. When an adequate thermal budget does not exist, the amount of activated doping concentration adjacent the channel does not suffice. Further, gate doping typically occurs prior to the formation of source and drain electrodes by implantation. Subsequent multiple implant steps and anneals are required to complete formation of the transistor. This further processing negatively affects and modifies the electrical properties of polysilicon gates and adversely alters the transistor's performance and reliability. In conventional transistor fabrication with a source/drain stressor, multiple material etching/deposition steps take place which negatively impact the polysilicon gate integrity.
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